The present invention relates generally to integrated circuit memory devices and, more particularly, to improving random access cycle time for Dynamic Random Access Memories (DRAMs).
The evolution of sub-micron CMOS technology has resulted in significant improvement in microprocessor speeds. Quadrupling roughly every three years, microprocessor speeds have now even exceeded 1 Ghz. Along with these advances in microprocessor technology have come more advanced software and multimedia applications, requiring larger memories for the application thereof. Accordingly, there is an increasing demand for larger Dynamic Random Access Memories (DRAMs) with higher density and performance.
DRAM architectures have evolved over the years, being driven by system requirements that necessitate larger memory capacity. However, the speed of a DRAM, characterized by its random access time (tRAC) and its random access cycle time (tRC), has not improved in a similar fashion. As a result, there is a widening speed gap between the DRAMs and the CPU, since the clock speed of the CPU steadily improves over time.
The random access cycle time (tRC) of a DRAM array is generally determined by the array time constant, which represents the amount of time to complete all of the random access operations. Such operations include: wordline activation, signal development on the bitlines, bitline sensing, signal write back, wordline deactivation and bitline precharging. Because these operations are performed sequentially in a conventional DRAM architecture, increasing the transfer speed, or bandwidth, of the DRAM becomes problematic.
The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by a memory cell system for a dynamic random access memory (DRAM) array. In an exemplary embodiment of the invention, the system includes a plurality of data storage elements arranged in rows and columns. A plurality of wordlines corresponds to the columns, and a plurality of lower bit lines corresponds to the rows, with each of the plurality of lower bitlines further being associated with a plurality of upper, complementary bitlines thereto. The plurality of upper bitlines are vertically aligned with the plurality of lower bitlines, thereby defining a plurality of vertically folded bitline pairs. Further, a plurality of sense amplifiers are arranged in the rows, with each of said plurality of sense amplifiers having one of said plurality of vertically folded bitline pairs as inputs thereto. When one of the plurality of wordlines is activated, a subset of the rows corresponding to the vertically folded bitline pairs is activated.
In a preferred embodiment, when one of the plurality of wordlines is activated, only every other of the rows corresponding to the vertically folded bitline pairs is activated. In addition, the plurality of data storage elements are arranged in a non-cross point configuration with respect to the rows and columns. One group of the sense amplifiers is arranged on one side of the array, while another group of the sense amplifiers is arranged on the opposite side of the array. When one group of the sense amplifiers is activated, the other group of sense amplifiers is deactivated. Correspondingly, when the other group of sense amplifiers is activated, the one group of sense amplifiers is deactivated.